1. Technical Field
The present invention relates generally to an improved data processing system and in particular to computer aided engineering programs. Still more particularly, the present invention relates to an improved method and apparatus for verification of digital circuits.
2. Description of the Related Art
Much of the process of creating, testing, and implementing an electronic circuit has been automated by the use of computers as a design tool. The computer executes a design or engineering program that provides a human user with tools such as "capturing" a design into electronic form, editing the design with the computer, detecting errors in the design, simulating the operation of the design and translating the design into a component layout or integrated circuit mask pattern depending on the final implementation. The availability of efficient, user-friendly software tools to aid the designer has become very important as the size and complexity of circuits designs increases.
One function provided by computer aided design tools is automatic synthesis and optimization of a circuit design from a schematic diagram. The computer aided design (CAD) system is given a set of constraints, such as timing specifications, and produces a circuit that performs the logic of the schematic diagram while meeting the specified constraints. A typical constraint is, e.g., minimum propagation delay from an input to an output. The CAD system may have to improve the speed of portions of the design by implementing logic functions in combinatorial logic as opposed to standard cells, by using faster logic families or by reducing the number of components used to achieve time critical logic functions.
The synthesis and optimization of a design from a schematic diagram can be complex and time consuming both to the human designer and to the computer's resources where the circuit of the schematic diagram is large and the constraints are many and stringent. Further, requiring the designer to specify constraints to the computer program in the first place can be very burdensome and time consuming. The designer must evaluate many factors including, for example, signal relationships, manufacturing costs, the timing of external signals that the circuit must interface with, and tolerances of components used in the circuit.
Asynchronous logic circuits are present in and critical in the design of low power, delay sensitive, high performance digital circuits. Typically, asynchronous logic circuits are used in real time applications involving digital communication and computer systems. Although there are some automated methodologies which can provide machine design of some types of asynchronous circuits, heretofore no practical automated methodology has existed which could successfully provide design solutions for real applications. Therefore, the solution of complex asynchronous circuit design problems always required intuition and experience, and was consequently a difficult and error prone task. Often the design of the asynchronous circuit entails a substantial amount of time to debug.
Historically, dynamic simulations have been used to verify circuit functionality and timing. Dynamic simulation rely on vectors for the simulation of functionality and timing. However, due to increasing design complexities it is virtually impossible to fully verify a circuit with dynamic simulations because of the size of the vectors needed to simulate each state of the circuit. Static timing analysis tools which do not rely on vectors have been developed to verify circuit timing. Static timing analysis tools have the capability to verify circuit timings more completely and efficiently because they can analyze all possible timing paths, provided the design synchronous. For pure synchronous designs, static timing analysis can verify 100% of all timing paths. However, static timing analysis can not fully verify non-synchronous circuits such as circuits with glitches, asynchronous clocks or other types of hazards that can cause the circuit to fail. Presently, this limitation still requires that dynamic timing simulations be used to verify these type of non-synchronous circuits. Even with dynamic timing simulation it is difficult to fully verify a circuit for these type of non-synchronous hazards because it is virtually impossible to simulate enough patterns to identify all possible hazards in the circuit.
Therefore, it would be advantageous to have an improved method and apparatus for analyzing asynchronous circuits.